Protecting the footprint of memory transactions from victimization

ABSTRACT

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

PRIORITY CLAIM

This application is a continuation of U.S. patent application Ser. No.13/967,853 entitled “PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONSFROM VICTIMIZATION,” filed on Aug. 15, 2013, the disclosure of which isincorporated herein by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

The present invention relates generally to data processing and, inparticular, to storage accesses to the distributed shared memory systemof a data processing system.

A conventional multiprocessor (MP) computer system, such as a servercomputer system, includes multiple processing units all coupled to asystem interconnect, which typically comprises one or more address, dataand control buses. Coupled to the system interconnect is a systemmemory, which represents the lowest level of volatile memory in themultiprocessor computer system and which generally is accessible forread and write access by all processing units. In order to reduce accesslatency to instructions and data residing in the system memory, eachprocessing unit is typically further supported by a respectivemulti-level cache hierarchy, the lower level(s) of which may be sharedby one or more processor cores.

Cache memories are commonly utilized to temporarily buffer memory blocksthat might be accessed by a processor in order to speed up processing byreducing access latency introduced by having to load needed data andinstructions from system memory. In some MP systems, the cache hierarchyincludes at least two levels. The level one (L1) or upper-level cache isusually a private cache associated with a particular processor core andcannot be accessed by other cores in an MP system. Typically, inresponse to a memory access instruction such as a load or storeinstruction, the processor core first accesses the directory of theupper-level cache. If the requested memory block is not found in theupper-level cache, the processor core then accesses lower-level caches(e.g., level two (L2) or level three (L3) caches) or system memory forthe requested memory block. The lowest level cache (e.g., L3 cache) isoften shared among several processor cores.

In such systems, multiprocessor software concurrently accesses shareddata structures from multiple software threads. When concurrentlyaccessing shared data it is typically necessary to prevent so-called“unconstrained races” or “conflicts”. A conflict occurs between twomemory accesses when they are to the same memory location and at leastone of them is a write and there is no means to ensure the ordering inwhich those accesses occur.

Multiprocessor software typically utilizes lock variables to coordinatethe concurrent reading and modifying of locations in memory in anorderly conflict-free fashion. A lock variable is a location in memorythat is read and then set to a certain value, possibly based on thevalue read, in an atomic fashion. The read-modify-write operation on alock variable is often accomplished utilizing anatomic-read-modify-write (ARMW) instruction or by a sequence ofinstructions that provide the same effect as a single instruction thatatomically reads and modifies the lock variable.

In this manner, a software thread reading an initial “unlocked” valuevia an ARMW instruction is said to have “acquired” the lock and will,until it releases the lock, be the only software thread that holds thelock. The thread holding the lock may safely update the shared memorylocations protected by the lock without conflict with other threadsbecause the other threads cannot obtain the lock until the currentthread releases the lock. When the shared locations have been readand/or modified appropriately, the thread holding the lock releases thelock (e.g., by writing the lock variable to the “unlocked” value) toallow other threads to access the shared locations in storage.

While locking coordinates competing threads' accesses to shared data,locking suffers from a number of well known shortcomings. These include,among others, (1) the possibility of deadlock when a given thread holdsmore than one lock and prevents the forward progress of other threadsand (2) the performance cost of lock acquisition when the lock may nothave been strictly necessary because no conflicting accesses would haveoccurred to the shared data.

To overcome these limitations, the notion of transactional memory can beemployed. In transactional memory, a set of load and/or storeinstructions are treated as a “transaction.” A transaction succeeds whenthe constituent load and store operations can occur atomically without aconflict with another thread. The transaction fails in the presence of aconflict with another thread and can then be re-attempted. If atransaction continues to fail, software may fall back to using lockingto ensure the orderly access of shared data.

To support transactional memory, the underlying hardware tracks thestorage locations involved in the transaction—the transactionfootprint—as the transaction executes for conflicts. If a conflictoccurs in the transaction footprint, the transaction is aborted andpossibly restarted. Use of transactional memory reduces the possibilityof deadlock due to a thread holding multiple locks because, in thetypical case, no locks are held (the transaction simply attempts to makeone or more storage accesses and restarts if a conflict occurs).Further, the processing overhead of acquiring a lock is generallyavoided.

BRIEF SUMMARY

A processing unit includes a processor core and a cache memory. Entriesin the cache memory are grouped in multiple congruence classes. Thecache memory includes tracking logic that tracks a transaction footprintincluding cache line(s) accessed by transactional memory accessrequest(s) of a memory transaction. The cache memory, responsive toreceiving a memory access request that specifies a target cache linehaving a target address that maps to a congruence class, forms a workingset of ways in the congruence class containing cache line(s) within thetransaction footprint and updates a replacement order of the cache linesin the congruence class. Based on membership of the at least one cacheline in the working set, the update promotes at least one cache linethat is not the target cache line to a replacement order position inwhich the at least one cache line is less likely to be replaced.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a high-level block diagram of an exemplary data processingsystem in accordance with one embodiment;

FIG. 2 is a more detailed block diagram of an exemplary processing unitin accordance with one embodiment;

FIG. 3 is a detailed block diagram of lower level cache supportingmemory transactions in accordance with one embodiment;

FIG. 4 is an illustrative example of a memory transaction in accordancewith one embodiment;

FIG. 5 is an illustrative example of a memory transaction including asuspended region in accordance with one embodiment;

FIG. 6A depicts execution of an exemplary program illustrating causalityin a multiprocessor data processing system;

FIG. 6B illustrates execution of an exemplary program including memorytransactions to ensure causality;

FIG. 6C depicts execution of an exemplary program including bothtransactional and non-transactional memory accesses;

FIG. 7 illustrates a multiprocessor data processing system including atleast three processor cores that execute the exemplary program of FIG.6C;

FIG. 8 is a high level logical flowchart of an exemplary method by whicha multiprocessor data processing system ensures causality in executionof a program including both transactional and non-transactional memoryaccesses;

FIG. 9 is an illustrative example of a rewind-only memory in accordancewith one embodiment;

FIG. 10 is more detailed view of transactional memory tracking logic inaccordance with one embodiment;

FIG. 11 is a high level logical flowchart of an exemplary method bywhich a rewind-only transaction is processed in accordance with oneembodiment;

FIG. 12 is an illustrative example of a representative memorytransaction containing a nested memory transaction in accordance withone embodiment;

FIG. 13 is an illustrative example of a representative rewind-onlymemory transaction containing a nested memory transaction in accordancewith one embodiment;

FIG. 14 illustrates a portion of transaction memory (TM) tracking logicthat may be employed in processing nested memory transactions inaccordance with one embodiment;

FIG. 15 is a high level logical flowchart of an exemplary method ofprocessing instructions delimiting nested memory transactions inaccordance with one embodiment;

FIG. 16 is a high level logical flowchart of an exemplary method bywhich a cache memory protects the footprint of a memory transaction fromvictimization by selectively updating replacement order (e.g., LRU)information in the cache directory; and

FIG. 17 is a data flow diagram illustrating a design process.

DETAILED DESCRIPTION

With reference now to the figures, wherein like reference numerals referto like and corresponding parts throughout, and in particular withreference to FIG. 1, there is illustrated a high level block diagramdepicting an exemplary data processing system 100 in accordance with oneembodiment. In the depicted embodiment, data processing system 100 is acache coherent symmetric multiprocessor (SMP) data processing systemincluding multiple processing nodes 102 a, 102 b for processing data andinstructions. Processing nodes 102 are coupled to a system interconnect110 for conveying address, data and control information. Systeminterconnect 110 may be implemented, for example, as a busedinterconnect, a switched interconnect or a hybrid interconnect.

In the depicted embodiment, each processing node 102 is realized as amulti-chip module (MCM) containing four processing units 104 a-104 d,each preferably realized as a respective integrated circuit. Theprocessing units 104 within each processing node 102 are coupled forcommunication to each other and system interconnect 110 by a localinterconnect 114, which, like system interconnect 110, may beimplemented, for example, with one or more buses and/or switches. Systeminterconnect 110 and local interconnects 114 together form a systemfabric.

As described below in greater detail with reference to FIG. 2,processing units 104 each include a memory controller 106 coupled tolocal interconnect 114 to provide an interface to a respective systemmemory 108. Data and instructions residing in system memories 108 cangenerally be accessed, cached and modified by a processor core in anyprocessing unit 104 of any processing node 102 within data processingsystem 100. System memories 108 thus form the lowest level of volatilestorage in the distributed shared memory system of data processingsystem 100. In alternative embodiments, one or more memory controllers106 (and system memories 108) can be coupled to system interconnect 110rather than a local interconnect 114.

Those skilled in the art will appreciate that SMP data processing system100 of FIG. 1 can include many additional non-illustrated components,such as interconnect bridges, non-volatile storage, ports for connectionto networks or attached devices, etc. Because such additional componentsare not necessary for an understanding of the described embodiments,they are not illustrated in FIG. 1 or discussed further herein. Itshould also be understood, however, that the enhancements describedherein are applicable to cache coherent data processing systems ofdiverse architectures and are in no way limited to the generalized dataprocessing system architecture illustrated in FIG. 1.

Multiprocessor data processing system such as data processing system 100of FIG. 1 implement a memory consistency model that specifies the legalpossible executions of a given multiprocessor program with respect tomemory accesses (e.g., among other things, the values that may bereturned by load instructions, the order of writes to memory, thoseinstruction execution dependencies that affect the ordering of memoryaccesses, and the final values for memory locations at the conclusion ofa multiprocessor program). A memory consistency model is specified bytwo major characteristics: ordering of memory access operations andatomicity of store operations.

The ordering of memory operations specifies how memory operations may,if at all, be re-ordered relative to the order of their respective loadand store instructions in the individual threads of execution in themultiprocessor program. Memory consistency models must define orderingof memory access operations in four general cases: (1) ordering of thememory operations for a load instruction to a following loadinstruction, (2) ordering of the memory operations for a loadinstruction to a following store instruction, (3) ordering of the memoryoperations for a store instruction to a following store instruction, and(4) ordering of the memory operations for a store instruction to afollowing load instruction. Strong consistency memory models will, ingeneral, preserve all or at least most of these orderings. Inparticular, many strong consistency memory models enforce the firstthree orderings, but do not enforce store-to-load ordering. Weakconsistency memory models will generally not enforce most or all ofthese orderings.

Atomicity of store operations refers to whether or not a given thread ofexecution can read the value of its own store operation before otherthreads, and furthermore, whether the value written to the distributedshared memory system by the store operation becomes visible to otherthreads in a logically instantaneous fashion or whether the value canbecome visible to other threads at different points in time. A memoryconsistency model is called “multi-copy atomic” if the value written bya store operation of one thread becomes visible to all other threads ina logically instantaneous fashion. In general, strong consistency memorymodels are multi-copy atomic, and weak consistency memory models do notenforce multi-copy atomicity.

In a given multiprocessor program, program semantics often require thatmulti-copy atomicity and/or the various orderings between memory accessoperations are respected. Therefore, in a data processing system 100having a distributed shared memory system that implements a weakconsistency memory model, so called “barrier” (e.g., SYNC) instructionsare typically provided to allow the programmer to specify what memoryaccess operation orderings and atomicity are to be applied duringexecution of the multiprocessor program.

Referring now to FIG. 2, there is depicted a more detailed block diagramof an exemplary processing unit 104 in accordance with one embodiment.In the depicted embodiment, each processing unit 104 is an integratedcircuit including two or more processor cores 200 a, 200 b forprocessing instructions and data. In a preferred embodiment, eachprocessor core 200 is capable of independently executing multiplehardware threads of execution simultaneously. However, in the followingdescription, unless the interaction between threads executing on a sameprocessor core is relevant in a particular context, for simplicity,terms “processor core” and “thread executing on a processor core” areused interchangeably. As depicted, each processor core 200 includes oneor more execution units, such as load-store unit (LSU) 202, forexecuting instructions. The instructions executed by LSU 202 includememory access instructions that request load or store access to a memoryblock in the distributed shared memory system or cause the generation ofa request for load or store access to a memory block in the distributedshared memory system. Memory blocks obtained from the distributed sharedmemory system by load accesses are buffered in one or more registerfiles (RFs) 208, and memory blocks updated by store accesses are writtento the distributed shared memory system from the one or more registerfiles 208.

The operation of each processor core 200 is supported by a multi-levelvolatile memory hierarchy having at its lowest level a shared systemmemory 108 accessed via an integrated memory controller 106, and at itsupper levels, one or more levels of cache memory, which in theillustrative embodiment include a store-through level one (L1) cache 226within and private to each processor core 200, and a respective store-inlevel two (L2) cache 230 for each processor core 200 a, 200 b. In orderto efficiently handle multiple concurrent memory access requests tocacheable addresses, each L2 cache 230 can be implemented with multipleL2 cache slices, each of which handles memory access requests for arespective set of real memory addresses.

Although the illustrated cache hierarchies includes only two levels ofcache, those skilled in the art will appreciate that alternativeembodiments may include additional levels (L3, L4, etc.) of on-chip oroff-chip, private or shared, in-line or lookaside cache, which may befully inclusive, partially inclusive, or non-inclusive of the contentsthe upper levels of cache.

Each processing unit 104 further includes an integrated and distributedfabric controller 216 responsible for controlling the flow of operationson the system fabric comprising local interconnect 114 and systeminterconnect 110 and for implementing the coherency communicationrequired to implement the selected cache coherency protocol. Processingunit 104 further includes an integrated I/O (input/output) controller214 supporting the attachment of one or more I/O devices (not depicted).

In operation, when a hardware thread under execution by a processor core200 includes a memory access instruction requesting a specified memoryaccess operation to be performed, LSU 202 executes the memory accessinstruction to determine the target address (e.g., an effective address)of the memory access request. After translation of the target address toa real address, L1 cache 226 is accessed utilizing the target address.Assuming the indicated memory access cannot be satisfied solely byreference to L1 cache 226, LSU 202 then transmits the memory accessrequest, which includes at least a transaction type (ttype) (e.g., loador store) and the target real address, to its affiliated L2 cache 230for servicing.

With reference now to FIG. 3, there is illustrated a more detailed blockdiagram of an exemplary embodiment of a lower level cache (e.g., an L2cache 230) that supports memory transactions in accordance with oneembodiment. As shown in FIG. 3, L2 cache 230 includes a cache array 302and a directory 308 of the contents of cache array 302. Although notexplicitly illustrated, cache array 302 preferably is implemented with asingle read port and single write port to reduce the die area requiredto implement cache array 302.

Assuming cache array 302 and directory 308 are set associative as isconventional, memory locations in system memories 108 are mapped toparticular congruence classes within cache array 302 utilizingpredetermined index bits within the system memory (real) addresses. Theparticular memory blocks stored within the cache lines of cache array302 are recorded in cache directory 308, which contains one directoryentry for each cache line. While not expressly depicted in FIG. 3, itwill be understood by those skilled in the art that each directory entryin cache directory 308 includes various fields, for example, a tag fieldthat identifies the real address of the memory block held in thecorresponding cache line of cache array 302, a state field that indicatethe coherency state of the cache line, and inclusivity bits indicatingwhether the memory block is held in the associated L1 cache 226.

The information in cache directory 308 further includes replacementorder information, indicating a relative replacement order of theentries in each congruence class. Although a variety of replacementpolicies and corresponding replacement orderings may be employed, theembodiment of L2 cache 230 shown in FIG. 3 utilizes an LRU (LeastRecently Used) replacement policy and accordingly maintains LRUreplacement order information 309 indicating a relative replacementorder for the set of cache lines in each congruence class. In aconventional implementation of the LRU replacement policy, the cachelines are ordered in accordance with how recently they have beenaccessed, from the most recently used (MRU) cache line, which is leastlikely to be replaced, to the least recently used (LRU) cache line,which is most likely to be replaced. The replacement ordering of thecache lines between LRU and MRU are commonly described with reference tothe likelihood of selection for replacement (victimization) as LRU,LRU+1, LRU+2, . . . , MRU−2, MRU−1, MRU.

In a conventional implementation of the LRU replacement policy, a cacheupdates the replacement order of the cache lines in a congruence classin response to each memory access request specifying a real address thatmaps to that congruence class, with the accessed cache line beingdesignated as the MRU cache line and, if necessary, the LRU cache linebeing replaced and each other cache line in the congruence class beingdemoted one position (e.g., LRU+1 to LRU and so on). In a preferredembodiment of L2 cache 230, directory 308 does not implement theconventional LRU replacement policy, but instead implements a modifiedLRU replacement policy that favors retention, within L2 cache 230, ofcache lines in the footprint of a memory transaction.

L2 cache 230 includes multiple (e.g., 16) Read-Claim (RC) machines 312for independently and concurrently servicing load (LD) and store (ST)requests received from the affiliated processor core 200. In order toservice remote memory access requests originating from processor cores200 other than the affiliated processor core 200, L2 cache 230 alsoincludes multiple snoop machines 311. Each snoop machine 311 canindependently and concurrently handle a remote memory access request“snooped” from local interconnect 114. As will be appreciated, theservicing of memory access requests by RC machines 312 may require thereplacement or invalidation of memory blocks within cache array 302.Accordingly, L2 cache 230 also includes CO (castout) machines 310 thatmanage the removal and writeback of memory blocks from cache array 302.

L2 cache 230 further includes an arbiter 305 that controls multiplexersM1-M2 to order the processing of local memory access requests and memorytransaction requests (corresponding to the tbegin, tbegin_rot, tend,tabort, and tcheck instructions described further herein) received fromthe affiliated processor core 200 and remote requests snooped on localinterconnect 114. Such requests, including local load and store andmemory transaction requests and remote load and store requests, areforwarded in accordance with the arbitration policy implemented byarbiter 305 to dispatch logic, such as a dispatch pipeline 306, whichprocesses each read/load and store request with respect to directory 308and cache array 302. As described further below, transactional memory(TM) logic 380 processes memory transaction requests and tracks memoryaccess operations within memory transactions to ensure completion of thememory access operations in an atomic manner or to abort the memorytransactions in the presence of conflicts.

L2 cache 230 also includes an RC queue 320 and a CPI (castout pushintervention) queue 318 that respectively buffer data being insertedinto and removed from the cache array 302. RC queue 320 includes anumber of buffer entries that each individually correspond to aparticular one of RC machines 312 such that each RC machine 312 that isdispatched retrieves data from only the designated buffer entry.Similarly, CPI queue 318 includes a number of buffer entries that eachindividually correspond to a particular one of the castout machines 310and snoop machines 311, such that each CO machine 310 and each snooper311 that is dispatched retrieves data from only the respectivedesignated CPI buffer entry.

Each RC machine 312 also has assigned to it a respective one of multipleRC data (RCDAT) buffers 322 for buffering a memory block read from cachearray 302 and/or received from local interconnect 114 via reload bus323. The RCDAT buffer 322 assigned to each RC machine 312 is preferablyconstructed with connections and functionality corresponding to thememory access requests that may be serviced by the associated RC machine312. RCDAT buffers 322 have an associated store data multiplexer M4 thatselects data bytes from among its inputs for buffering in the RCDATbuffer 322 in response unillustrated select signals generated by arbiter305.

In operation, a processor core 200 transmits store requests comprising atransaction type (ttype), target real address and store data to a storequeue (STQ) 304. From STQ 304, the store data are transmitted to storedata multiplexer M4 via data path 324, and the transaction type andtarget address are passed to multiplexer M1. Multiplexer M1 alsoreceives as inputs processor load requests from processor core 200 anddirectory write requests from RC machines 312. In response tounillustrated select signals generated by arbiter 305, multiplexer M1selects one of its input requests to forward to multiplexer M2, whichadditionally receives as an input a remote request received from localinterconnect 114 via remote request path 326. Arbiter 305 scheduleslocal and remote memory access requests for processing and, based uponthe scheduling, generates a sequence of select signals 328. In responseto select signals 328 generated by arbiter 305, multiplexer M2 selectseither the local request received from multiplexer M1 or the remoterequest snooped from local interconnect 114 as the next memory accessrequest to be processed.

The request selected for processing by arbiter 305 is placed bymultiplexer M2 into dispatch pipeline 306. Dispatch pipeline 306preferably is implemented as a fixed duration pipeline in which each ofmultiple possible overlapping requests is processed for a predeterminednumber of clock cycles (e.g., 4 cycles). During the first cycle ofprocessing within dispatch pipeline 306, a directory read is performedutilizing the request address to determine if the request address hitsor misses in directory 308, and if the memory address hits, thecoherency state of the target memory block. The directory information,which includes a hit/miss indication and the coherency state of thememory block, is returned by directory 308 to dispatch pipeline 306 in asubsequent cycle. As will be appreciated, no action is generally takenwithin an L2 cache 230 in response to miss on a remote memory accessrequest; such remote memory requests are accordingly discarded fromdispatch pipeline 306. However, in the event of a hit or miss on a localmemory access request or a hit on a remote memory access request, L2cache 230 will service the memory access request, which for requeststhat cannot be serviced entirely within processing unit 104, may entailcommunication on local interconnect 114 via fabric controller 216.

At a predetermined time during processing of the memory access requestwithin dispatch pipeline 306, arbiter 305 transmits the request addressto cache array 302 via address and control path 330 to initiate a cacheread of the memory block specified by the request address. The memoryblock read from cache array 302 is transmitted via data path 342 toError Correcting Code (ECC) logic 344, which checks the memory block forerrors and, if possible, corrects any detected errors. For processorload requests, the memory block is also transmitted to load datamultiplexer M3 via data path 340 for forwarding to the affiliatedprocessor core 200.

At the last cycle of the processing of a memory access request withindispatch pipeline 306, dispatch pipeline 306 makes a dispatchdetermination based upon a number of criteria, including, for example,(1) the presence of an address collision between the request address anda previous request address currently being processed by a castoutmachine 310, snoop machine 311 or RC machine 312, (2) the directoryinformation, and (3) availability of an RC machine 312 or snoop machine311 to process the memory access request. If dispatch pipeline 306 makesa dispatch determination that the memory access request is to bedispatched, the memory access request is dispatched from dispatchpipeline 306 to an RC machine 312 or a snoop machine 311. If the memoryaccess request fails dispatch, the failure is signaled to the requestor(e.g., local or remote processor core 200) by a retry response. Therequestor may subsequently retry the failed memory access request, ifnecessary.

While an RC machine 312 is processing a local memory access request, theRC machine 312 has a busy status and is not available to service anotherrequest. While an RC machine 312 has a busy status, the RC machine 312may perform a directory write to update the relevant entry of directory308, if necessary. In addition, the RC machine 312 may perform a cachewrite to update the relevant cache line of cache array 302. Directorywrites and cache writes may be scheduled by arbiter 305 during anyinterval in which dispatch pipeline 306 is not already processing otherrequests according to the fixed scheduling of directory reads and cachereads. When all operations for the given request have been completed,the RC machine 312 returns to an unbusy state.

Associated with RC machines 312 is data handling circuitry, differentportions of which are employed during the servicing of various types oflocal memory access requests. For example, for a local load request thathits in directory 308, an uncorrected copy of the target memory block isforwarded from cache array 302 to the affiliated processor core 200 viadata path 340 and load data multiplexer M3 and additionally forwarded toECC logic 344 via data path 342. In the case of an ECC error in thetarget memory block obtained by the local load request, corrected datais forwarded to RCDAT buffer 322 via data path 346 and store datamultiplexer M4 and then from RCDAT 322 to affiliated processor core 200via data path 360 and load data multiplexer M3. For a local storerequest, store data is received within RCDAT buffer 322 from STQ 304 viadata path 324 and store data multiplexer M4, the store is merged withthe memory block read into RCDAT buffer 322 from cache array 302 via ECClogic 344 and store data multiplexer M4, and the merged store data isthen written from RCDAT buffer 322 into cache array 302 via data path362. In response to a local load miss or local store miss, the targetmemory block acquired through issuing a memory access operation on localinterconnect 114 is loaded into cache array 302 via reload bus 323,store data multiplexer M4, RCDAT buffer 322 (with store merge for astore miss) and data path 362.

Referring now to FIG. 4, an illustrative example of a memory transactionis depicted. Those skilled in the art will recognize that the particularsemantics and instructions utilized to implement the various memorytransactions described herein are but some of the numerous possibleimplementations and that the disclosed techniques of implementingtransactional memory are not dependent on the specific instructions andinstruction semantics employed.

Illustrative memory transaction 400 begins at tbegin instruction 402.Tbegin instruction 402 initiates memory transaction 400, causes theprocessor core 200 executing tbegin instruction 402 to take a checkpoint210 of the architected register state of processor core 200, and (e.g.,through a corresponding tbegin request sent to the affiliated L2 cache230) invokes tracking of load and store instructions within thetransaction body 406 to ensure they complete in an atomic fashion orthat memory transaction 400 fails in the presence of a conflict. Memorytransaction 400 additionally includes a branch instruction 404immediately following tbegin instruction 402. When memory transaction400 first executes, the condition code register in processor core 200upon which branch instruction 404 depends is initialized to a value thatcauses the program branch indicated by branch instruction 404 not to betaken and the flow of execution to continue to transaction body 406. Asdiscussed below, in response to failure of memory transaction 400, thecondition code register is set to a different value, and branchinstruction 404 causes execution to branch to a fail handler routine.

In the exemplary embodiment depicted in FIG. 3, TM logic 380 trackstransactional memory access (e.g., load and store) instructions withintransaction body 406 to ensure that they complete in an atomic fashionor that memory transaction 400 fails in the presence of a conflict. In apreferred embodiment, TM tracking logic 381 within TM logic 380 includesa number of entries that indicate which cache lines in cache array 302are included in the transaction footprint (as described below, forexample, with reference to FIG. 10). The transaction footprint includestwo portions: the load footprint corresponding to cache lines touchedsolely by loads within transaction body 406 (e.g., the cache line ataddress A in exemplary memory transaction 400) and the store footprintcorresponding to cache lines touched solely by store instructions or byboth load and store instructions in transaction body 406 (e.g., thecache line at address B in exemplary memory transaction 400). In apreferred embodiment, TM tracking logic 381 attempts to keep thetransaction footprint resident in L2 cache 230 in the presence ofvarious transactional and non-transactional memory access request of thethreads of processor core 200 by providing to directory 308 replacementorder update messages 383 that make selection of cache lines in thetransaction footprint for victimization (castout) less likely.

As further shown in FIG. 3, TM logic 380 further includes transactionalcontrol logic 382, which controls the sequencing of a memory transactionand provides a pass/fail indication 384 and an optional TM killedindication 385 to the associated processor core 200. Pass/failindication 384 indicates to processor core 200 whether or not the memorytransaction successfully committed to the distributed shared memorysystem at the execution of the tend instruction 408 at the end of memorytransaction 400. TM killed indication 385 indicates to processor core200 whether or not a conflict has occurred during the transaction. Inresponse to transactional control logic 382 asserting TM killedindication 385, processor core 200 may, as a performance optimization,optionally abort and restart memory transaction 400 prior to reachingtend instruction 408. In at least some embodiments in which TM trackinglogic 381 only tracks cache lines resident in L2 cache 230 and does nottrack cache lines following eviction, TM logic 380 additionally assertsTM killed indication 385 for a memory transaction in response toeviction from L2 cache 230 of a cache line in the transaction footprintof the memory transaction. Pessimistically killing memory transactionsfor which one or more cache lines in the transaction footprint can nolonger be tracked ensures that the semantics of the memory transactionare properly observed.

In response to pass/fail indication 384 (or optionally TM killedindication 385) indicating that a conflict has occurred during executionof memory transaction 400, processor core 200 re-establishes itsarchitected register state from the checkpoint 210 taken at theexecution of tbegin instruction 402, invalidates the tentativelymodified cache lines in the store footprint, releases tracking logic381, sets the condition code register such that branch instruction 404will be taken, and transfers control to branch instruction 404. Inaddition, processor core 200 sets a transaction failure cause register(not shown) in processor core 200 to indicate the cause of the memorytransaction's failure. The fail handler routine invoked by branchinstruction 404 may choose to re-attempt memory transaction 400 or fallback to more conventional locking mechanisms, optionally based on thecontent of the transaction failure cause register.

During the execution of a memory transaction, the values stored to thedistributed shared memory system by transaction body 406 (i.e., those inthe store footprint of the memory transaction) are visible only to thethread of the processor core 200 executing the memory transaction.Threads running on the same or other processor cores 200 will not seethese values until and only if the memory transaction successfullycommits.

For a memory transaction to successfully commit, the load and storeinstructions in transaction body 406 must complete in an atomic fashion(i.e., there must be no conflicts for the cache lines in the memorytransaction's load and store footprints) and the effects of the storeinstructions in transaction body 406 must propagate to all processingunits 104 in data processing system 100 and invalidate any cached copiesof those cache lines held in other processing units 104. If both ofthese conditions hold when tend instruction 408 is executed,transactional control logic 382 indicates to processor core 200 viapass/fail indication 384 that memory transaction 400 passed and commitsall stores performed in transaction body 406 to L2 cache 230, thusmaking them visible to all other threads and processor cores 200 in thesystem simultaneously.

In the following discussion, a load or store instruction will be called“transactional” if that load or store instruction occurs within thetransaction body 406 of a memory transaction 400. Similarly, a load orstore will be called “non-transactional” if it occurs outside atransaction body 406. In one exemplary embodiment, a conflict policy ofdata processing system 100 defines a conflict with another processorcore's memory access to occur for a given memory transaction in any oneof several possible cases. In a first case, a conflict occurs if anon-transactional store from another processor core 200 hits a cacheline within either the given memory transaction's load or storefootprint. In a second case, a conflict occurs if a transactional storefrom another processor core 200 hits a cache line within the givenmemory transaction's load footprint. In a third case, a conflict occursif a non-transactional load hits a cache line within the given memorytransaction's store footprint. In a fourth case, a conflict occurs if atransactional load from another processor core 200 hits a cache linewithin the given memory transaction's store footprint. In addition, thegiven memory transaction has a conflict if one of its transactionalstores hits an address already extant in the store footprint of anotherprocessor core's memory transaction. This exemplary conflict policy isbut one of several possible embodiments of transactional memory. Theabove conflict policy biases in favor of transactional stores overtransactional loads, while allowing transactional and non-transactionalloads to freely intermingle.

With reference now to FIG. 5, there is illustrated a representativememory transaction 500 containing a suspended region. As can be seen bycomparison of FIGS. 4-5, memory transaction 500 includes a tbegininstruction 502, branch instruction 504, transaction body 506 and tendinstruction 508, which correspond to tbegin instruction 402, branchinstruction 404, transaction body 406 and tend instruction 408 describedabove. In addition, memory transaction 500 includes a tsuspendinstruction 510 that initiates the start of a suspended region 512. Whena memory transaction is suspended through execution of tsuspendinstruction 510, the load and store footprints currently established forthe enclosing memory transaction containing suspended region 512 remainin place and continue to be tracked by TM tracking logic 381 forconflicts. However, any load or store instructions within suspendedregion 512 are treated as non-transactional loads and stores and followexisting semantics for such loads and stores. In particular, storeswithin suspended region 512 are non-transactional and will commit andbegin propagating to other processors unconditionally. If a store withinsuspended region 512 hits either the load or the store footprint of theenclosing memory transaction, a conflict occurs (which also destroys thetentative transactional version of the cache line in the storefootprint) and is logged by transactional control logic 382. However,this conflict is not acted on until the enclosing memory transaction isresumed upon execution of tresume instruction 514, at which point theprocessor core 200 passes control to branch instruction 504 asdescribed. If a non-transactional load instruction within suspendedregion 512 hits a cache line within the store footprint of the enclosingmemory transaction 500, that load instruction returns the tentativelyupdated value written by a transactional store within the transactionbody 506 unless that value has been overwritten by a non-transactionalstore either by another processor core 200 or by a non-transactionalstore in suspended region 512, in which case the non-transactional loadinstruction returns the current value of the target location.

Use of a suspended region 512 allows the temporary suspension of amemory transaction, which permits store instructions in the suspendedregion 512 to unconditionally update locations in the distributed sharedmemory system while also allowing for the resumption of the memorytransaction at a later time. One possible use for a suspended region 512is to log debug information into a scratchpad region of the distributedshared memory system and then to resume the enclosing memorytransaction. Without a suspended region, the write of the debuginformation would be rolled back any time the enclosing memorytransaction is aborted.

Referring now to FIG. 6A, the execution of an exemplary programillustrating the property of causality in a multiprocessor dataprocessing system is shown. As used herein “causality,” which isdesirable property in multiprocessor programs, is defined as beingpreserved if, during execution of a multiprocessor program, a giventhread of execution cannot read the effects of a computation before thewrites that caused the computation can be read by the given thread.

In the simplified example given in FIG. 6A (as well as those discussedbelow with reference to FIGS. 6B-6C), a multiprocessor program isexecuted by three processor cores 200 of data processing system 100,labeled for ease of reference as processor core 0, processor core 1 andprocessor core 2. In FIG. 6A, processor core 0 executes a storeinstruction 600 that writes a value of 1 to address A in the distributedshared memory system. This update of address A propagates to processorcore 1, and load instruction 610 executed by processor core 1 thereforereturns a value of 1. Even though the memory update made by storeinstruction 600 has propagated to processor core 1, that memory updatemay not yet have propagated to processor core 2. If store instruction614 executes on processor 1 and the associated memory update propagatesto processor 2 before the memory update of store instruction 600propagates to processor 2, causality would be violated because the storeof the value of 1 to address B, which is an effect of the store toaddress A, would be visible to processor core 2 before the memory updateassociated with causal store instruction 600 was visible to processorcore 2.

To ensure causality in a weak consistency memory model, barrierinstruction 612 (e.g., a SYNC) ensures that store instruction 614 doesnot take effect or begin propagating its memory update to otherprocessor cores until load instruction 610 has bound to its value. Inaddition, barrier instruction 612 also ensures that the memory updateassociated with store instruction 600 propagates to processor 2 beforethe memory update associated with store instruction 614. Thus, causalityis preserved because the cause of the computation (i.e., the memoryupdate of store instruction 600) is visible to processor core 2 beforethe result of the computation (i.e., the memory update of store 614). Abarrier instruction 622 is also executed by processor core 2 to ensurethat processor core 2 executes load instructions 620 and 624 and bindstheir values in order, thus guaranteeing that processor core 2 properlyobserves the memory updates made by processor core 0 and processor core1.

With reference now to FIG. 6B, an exemplary embodiment of themultiprocessor program of FIG. 6A rendered in terms of memorytransactions is illustrated. In FIG. 6B, the branch instructions to thememory transaction fail handler are omitted for clarity.

As illustrated, processor core 0 executes a memory transaction 630including a tbegin instruction 632, tend instruction 636, and atransaction body including a store instruction 634 that stores a valueof 1 to address A. Upon the execution of tend instruction 636, memorytransaction 600 successfully commits and makes the update to address Avisible to all the other processor cores simultaneously. In particular,by the time load instruction 642 of the memory transaction 640 executingon processor core 1 can read the value of 1 from address A, loadinstruction 654 of the memory transaction 650 executing on processorcore 2 must also be able to read the value of 1 for address A. Memorytransaction 640 then reads the value of 1 for address A, stores a valueof 1 to address B and successfully commits. Finally, load instruction652 of memory transaction 650 reads a value of 1 for address B, andgiven that memory transaction 640 read a value of 1 for A, loadinstruction 654 must also read a value of 1 for address A.

In order to make the memory updates of store instructions in asuccessful transaction visible to all other processor coressimultaneously, before that memory transaction can commit all the cacheline invalidates necessitated by the memory transaction must havepropagated through the data processing system such that any otherprocessor cores' now stale copies of the updated cache lines have beenremoved (e.g., invalidated) and can no longer be read by the otherprocessor cores. Without this requirement, a processor core could stillread a stale value for an updated memory location after the memorytransaction that updated the memory location committed. A processorcore, therefore, needs to ensure that the memory updates associated withits own transactional stores are fully propagated through the dataprocessing system to invalidate any stale cached copies beforecommitting a successful memory transaction in order to maintain thesemantics of memory transactions. As a consequence of the propagation ofthe memory updates inherent in the semantics of memory transactions,causality is trivially preserved when only memory transactions areutilized to access memory locations in a distributed shared memorysystem. However, when transactional and non-transactional code interacton the same shared variables, causality is not directly preserved byensuring that the memory updates made by a memory transaction arevisible simultaneously to all other processor cores.

Referring now to FIG. 6C, an illustrative multiprocessor program isdepicted that includes a mixture of transactional and non-transactionalaccesses to a distributed shared memory system. In the exemplarymultiprocessor program, processor core 0 executes a non-transactionalstore instruction 660 that unconditionally writes a value of 1 toaddress A in the distributed shared memory system. This value propagatesto processor core 1 and is read by transactional load instruction 672within the memory transaction 670 executed by processor core 1.Processor core 1 then executes a store instruction 674 within memorytransaction 670 that updates the cache line associated with address Band completes invalidating any stale cached copies of the cache lineassociated with address B (so that no other processor core holds a copyof the now stale cache line) and successfully commits memory transaction670 upon execution of tend instruction 676. Processor core 2 thenexecutes load instructions 680 and 684 to read, in order, the cachelines associated with addresses B and A, respectively, based on theordering enforced by barrier instruction 682. If transaction 670 onlyensures that its own memory updates are fully propagated through thedistributed shared memory system before committing, the memory update ofstore instruction 660 may or may not have propagated to processor core2. Therefore, in at least some operating scenarios, processor core 2could read a value of 1 for the cache line associated with address B andthe, now stale, initial value of 0 for the cache line associated withaddress A, thus violating causality. The same result would be obtainedif processor core 2 utilized transactional loads to read from addressesA and B, as depicted for processor 2 in FIG. 6B.

To guarantee causality, memory transaction 670 must ensure not only thatits own transactional stores are propagated throughout the entiredistributed shared memory system, but also that any non-transactionalstore that is read by a transactional load within the transaction hasalso propagated throughout the distributed shared memory system. (Memoryupdates of transactional writes that are read by the memory transactionare guaranteed to have propagated throughout the distributed sharedmemory system because those memory updates could not be read bytransaction 670 before they were visible to the entire distributedshared memory system). To ensure that the memory updates ofnon-transactional stores read by memory transaction 670 are alsopropagated throughout the distributed shared memory system, theprocessing of the tend instruction 676 of memory transaction 670 mustnot allow commitment of memory transaction 670 until the memory updateof any non-transactional store read by memory transaction 670 ispropagated throughout the distributed shared memory system.

With reference now to FIG. 7, there is illustrated a partial view ofdata processing system 100 of FIG. 1, which executes the multiprocessorprogram of FIG. 6C. In the view given in FIG. 7, processor cores 200 a,200 b and 200 c respectively correspond to processor cores 0, 1 and 2 ofFIG. 6C. Further, an instance of causality resolution logic 379 isinstantiated for and coupled to each instance of snooper 311, forexample, as a component of the L2 cache 230 affiliated with eachprocessor core 200.

Initially, processor core 200 c holds a cached copy of the initial value(e.g., 0) of memory location A in its L1 cache 226 c. Processor 200 abegins execution of the multiprocessor program of FIG. 6C by executingstore instruction 660. In response to execution of store instruction660, processor core 200 a transmits a store request to its L2 cache 230a, which allocates an RC machine 312 to service the store request. RCmachine 312 broadcasts the store request onto local interconnect 114,and snoop machine 311 c of the L2 cache 230 c affiliated with processorcore 200 c registers the store request, including the processing unitthat sourced the store request (i.e., the processing unit includingprocessor core 200 a). At this point, the memory update of storeinstruction 660 has not propagated to processor core 200 c, but isinstead queued for later processing, advantageously allowing processorcore 200 a to continue executing further instructions before the memoryupdate of store instruction 660 is fully propagated.

Processor core 200 b then executes load instruction 672 and, finding nocopy of the target cache line associated with address A in its L1 cache226 b, transmits a read request to its L2 cache 230 b. In response tothe read request, L2 cache 230 b allocates RC machine 312 b to servicethe read request. In response to a miss of the read request in L2 cache230 b, RC machine 312 b issues a read request onto local interconnect114 to obtain the current value for address A. L2 cache 230 a respondsto the read request and provides the current value of address A toprocessor core 200 b by cache-to-cache intervention. At this point aso-called “causality passing read” has occurred, that is, loadinstruction 672 has read the value of a store instruction that has notfully propagated through the entire distributed shared memory system. Toaccount for this fact and to protect causality, causality resolutionlogic 379 c in L2 cache 230 c notes the successful read interventionbetween the vertical cache hierarchies of processor cores 200 a and 200b for an address that is currently being invalidated by snoop machine311 c. In this manner causality resolution logic 379 c directly tracksthe causal dependency that processor 200 b and its vertical cachehierarchy has on the memory update of store instruction 660 completingits propagation.

Processor 200 b executes store instruction 674, which specifies anupdate of the value of address B to 1. In response to execution of storeinstruction 674, RC machine 312 b issues a store request correspondingto store instruction 674 on local interconnect 114. In absence of anexisting cached copy of the target cache line, memory controller 106supplies the current value of address B from system memory 108 inresponse to the store request, and RC machine 312 b updates L2 cache 230b accordingly. At this point processor core 1 executes tend instruction676 to attempt to successfully commit transaction 670 and places acorresponding TEND request on local interconnect 114 to ensure that allprior memory updates by transactional stores in memory transaction 670have been propagated throughout the distributed shared memory system andthat any memory updates by non-transactional stores read by memorytransaction 670 have similarly propagated throughout the distributedshared memory system. In this case, the memory update of storeinstruction 674 has fully propagated throughout the distributed sharedmemory system because no other caches held a copy of the cache lineassociated with address B. However, had any such copy existed and hadthe memory update not been fully complete, a snoop machine 311 in thosecaches, which noted the initial processor core 200 issuing the store,would be active and would provide a retry response to the snooped TENDrequest from that processor core 200 (forcing the TEND request to bereissued) until the invalidation of the cached copy of the cache linecompletes.

In the case at hand, the TEND request is not from the processor core 200that initiated the store request, and therefore snoop machine 311 c willnot provide a retry response to the TEND request. However, causalityresolution logic 379 c has a causal dependency for processor 200 b andits vertical cache hierarchy and issues on local interconnect 114 aretry response to the TEND request because the TEND request was issuedfrom a processor core 200 that was the recipient of a causality passingread of the same address that snoop machine 311 c is processing. In thismanner, causality resolution logic 379 directly tracks which processorcores 200 have a causality dependency due to reading a memory update ofa non-transactional store that was not fully completed for the processorcore with which causality resolution logic 379 is associated.

It should be noted that, in general, causality resolution logic 379 mustmaintain a list capable of representing all the processors cores 200 inthe data processing system to provide causality in cases in which thecausality dependency chain passes through more than one processor core(e.g., a test where a first processor stores a location, a secondprocessor reads that location and then stores a first flag variable, athird processor loads the first flag variable and writes a second flagin a transaction, and then a final thread reads the second flag and thenthe initial location). In such an implementation, a TEND request issuedfrom any processor core with a causal dependency on the target addressbeing invalidated by the snoop machine 311 associated with the instanceof causality resolution logic 379 is retried. In a large SMP, however,such an embodiment can be prohibitive in cost and many implementationsof causality resolution logic 379 only precisely track causal dependencychains of a certain fixed depth (e.g., two or three processors) and inthe presence of longer dependency chains resort to pessimisticallyretrying all TEND requests until the cache line invalidationsnecessitated by the store instruction have completed processing.

To summarize, causality resolution logic is utilized to detect theoccurrence of causal dependency chains, to a depth determined by theembodiment, on a pending store that has not completed processingthroughout the entire distributed shared memory system. These causaldependencies are utilized to stall the completion of TEND requests fromthose processor cores with a causal dependency on the incomplete(pending) stores. In this manner, the memory transaction cannot complete(and therefore make its own stores visible), until the stores the memorytransaction has read (i.e., those in the causal dependency chain of thememory transaction) have first completed throughout the distributedshared memory system. Only after these stores in the memorytransaction's causal dependency chain (and the transactional stores ofthe memory transaction itself, though this is guaranteed by snooper 311instead of causality resolution logic 379) have completed, may the TENDrequest complete, leading to the memory transaction successfullycommitting if no conflicts have occurred during its execution.

In other embodiments, additional causality resolution logic may berequired to ensure the causality of memory operations. For example, inan implementation that contains a write-through L1 cache shared by amultithreaded processor core followed by a shared L2 store queue, it ispossible for different threads (i.e., logically different processorcores from the point of view of software) to read stored values from theL1 cache before these stores have even propagated to the L2 cache, muchless to the entire distributed shared memory system. In such animplementation, the tend instruction must act as a barrier fortransactional stores in the given thread. This behavior ensures that thetransactional stores are propagated to the system interconnect and thenecessary snoop machines 311 so that the tend instruction can ensure,when trying to complete the memory transaction, that all of the cacheline invalidations required by the memory transaction's stores havefully propagated. In addition, the tend instruction must act as abarrier for non-transactional stores that have been (or may have been)read by transactional loads within the transaction. In the simplest (andmost common embodiment), all non-transactional stores within the sharedstore queue are treated as if they have come from a single thread forpurposes of retrying the TEND request.

In this manner, all non-transactional stores from which any transactionhas (or may have) read that have not been fully propagated are broadcastto snoop machines 311 as necessary before a TEND request for anytransaction from that multithreaded processor core is presented on localinterconnect 114. In such an embodiment, snoop machines 311 treat allstores coming from a given multithreaded processor core in a unifiedmanner and will retry any TEND request, as necessary, from that givenmultithreaded processor core regardless of thread. In this embodiment,causality resolution logic 379 is not involved in monitoring theseintra-core dependencies, but instead is utilized solely to managecausality dependencies between multithreaded processor cores.

The exact placement and details of the necessary causality resolutionlogic will vary with the particulars of given embodiment and will beapparent to those skilled in the art given the teachings herein. Ingeneral, at any point where a load may return the value of a store thathas not fully propagated throughout the entire distributed shared memorysystem, a mechanism must be provided to ensure that any store with acausal dependency to a different processor core is noted and that causaldependency delays the processing of a tend instruction (or othersemantic) ending a memory transaction until such time as the stores inthe causal dependency chain of the memory transaction have completedpropagating.

Referring now to FIG. 8, there is depicted a high level logicalflowchart of the processing of a tend instruction terminating a memorytransaction in accordance with one embodiment. The process begins atblock 800, for example, in response to initiation of execution of a tendinstruction within the LSU 202 of a processor core 200. The process ofFIG. 8 proceeds from block 800 to block 801, which depicts LSU 202ensuring that all prior suspend mode load instructions and all priortransactional load instructions have their values bound. This checkensures the transactional load instructions are present in the memorytransaction's footprint and that the suspend mode load instructions haveobtained their values. The process proceeds from block 801 to block 802,which depicts ensuring that the cache line invalidations necessitated bytransactional stores within the memory transaction have been fullypropagated throughout the distributed shared memory system. In theembodiment described above, verification of propagation of the cacheline invalidations necessitated by transactional stores is accomplishedby one or more snoop machines 311 providing a retry response to anyapplicable TEND request on local interconnect 114 until the previoustransactional stores have invalidated all cached copies of the memorylocation(s) targeted by the memory updates. The process then proceeds tostep 804, which illustrates ensuring that the cache line invalidationsnecessitated by causally dependent non-transactional stores havecompletely propagated throughout the distributed shared memory system.In the embodiment described above, verification of propagation of thecache line invalidations necessitated by non-transactional stores isaccomplished by one or more instances of causality resolution logic 379providing a retry response to any applicable TEND request on localinterconnect 114 until the previous memory updates of causally dependentnon-transactional stores have invalidated all cached copies of thememory location(s) targeted by the memory updates.

At block 806, transactional control logic 382 determines whether or nota conflict has occurred for the memory transaction. In response totransactional control logic 382 determining that a conflict hasoccurred, the process proceeds to block 808, which depicts transactionalcontrol logic 382 invalidating the tentative store footprint of thememory transaction (e.g., as recorded in L2 cache 230) and indicatingvia pass/fail indication 384 that the memory transaction has failed. Asfurther illustrated at block 808, in response to pass/fail indication384 processor core 200 updates its condition code register and transferscontrol to the fail handling branch instruction within the memorytransaction (block 808). The process then terminates at step 812.

Returning to block 806, in response to transactional control logic 382determining that no conflict has occurred during execution of the memorytransaction, the process proceeds to step 810, which depicts TM controllogic 382 committing the transaction, inter alia, by causing thetransaction footprint to be committed to the distributed shared memorysystem (e.g., by updating one or more coherence states in the directory308 of L2 cache 230 to indicate the transaction footprint is valid andavailable for access by all threads) and indicating to processor core200 via pass/fail indication 384 that the memory transaction passed. Theprocess then terminates at block 812.

Memory transactions, as described above, enable a programmer to enforceexecution of groups of load and/or store instructions by a dataprocessing system in an atomic fashion and to fail and repeat the memorytransactions as necessary to preserve the appearance of atomicity of thestorage accesses of the memory transactions in the presence of conflictswith other storage accesses. While memory transactions provide avaluable and needed capability, there is also a need to be able tospeculatively execute a block of instructions, particularly includingstore instructions, and then to be able to discard the results of thatexecution under software control without regard to the existence ofconflicting accesses. For example, some programming models require thatthe execution of certain code sequences do not cause a fault. To avoidsuch faults, an additional code sequence is typically required tovalidate that the inputs to the code sequence will not produce a faultbefore the sequence is executed. This pre-validation can incursignificant additional overhead. However, with a “rewind only”transaction (ROT) as described herein, the code sequence may bespeculatively executed without the additional overhead of validation andmay then be rewound if a fault occurs.

Discarding or “rewinding” the storage-modifying effects of a storeinstruction has traditionally not been supported in prior processors,and therefore the amount of speculation permitted for a storeinstruction (and for instructions dependent on that store instruction)was severely limited. As described herein, the mechanisms supportingtransactional memory may be adapted, reused and extended to efficientlysupport a discardable speculative execution mechanism for blocks ofinstructions, specifically those including store instructions. Withoutthe enhancements described herein, a full memory transaction would berequired to rewind store instructions, at additional cost as describedbelow.

To support rewinding the storage-modifying effects of storeinstructions, a distinct type of memory transaction referred to hereinas a “rewind only” transaction (ROT) is introduced. Unlike a traditionalmemory transaction, a ROT, by definition, does not require any conflictdetection or atomicity guarantees, but rather only provides a semanticto enforce the discarding of the execution results of a group of one ormore speculatively executed instructions that may include one or morestore instructions. Furthermore, the commitment of a ROT does not dependupon or require the propagation of the invalidations of causallydependent non-transactional stores through the distributed shared memorysystem, as described above with reference to block 804 of FIG. 8.

While conflict detection is not required for the semantic definition ofa ROT, a typical implementation will provide conflict tracking for storeinstructions within the ROT, if only to avoid additional unnecessarycomplexity in the design of the processor core and cache hierarchy atlittle additional benefit. So while conflict tracking is not requiredfor a ROT as a matter of definition (because atomicity is not preservedby a ROT), as a matter of implementation, hardware supporting executionof ROTs will typically provide conflict tracking for the store footprintof a ROT for simplicity.

The utility of retaining store footprint conflict tracking for ROTs canbe seen in the management of conflicts between different threads on amulti-threaded processor core sharing a common write-through L1 cache.In such a multi-threaded processor core, if multiple threads wereconcurrently executing ROTs including store instructions targeting agiven cache line, the L1 cache would have to be able to maintain adifferent image of the given cache line for each thread (i.e., the L1cache would have to be able to hold multiple concurrently active imagesof any given cache line). Furthermore, when each ROT committed, the L1cache would have to be able to merge the updates made to the cache lineby the thread committing the ROT into the remaining concurrent copy orcopies of the cache line—an operation that is exceptionally complex. Ingeneral, it is far more efficient and less costly to employ the existingconflict tracking mechanisms for the store footprint of a ROT as if itwere a non-ROT memory transaction.

Typically, load instructions will significantly outnumber storeinstructions in a memory transaction. For TM control logic 380 of agiven capacity, a significantly larger transaction can therefore beaccommodated as a ROT rather than a non-ROT memory transaction (which,in the absence of ROTs would have to be employed to rewind speculativelyexecuted store instructions). Furthermore, a ROT can successfullycomplete in the presence of false sharing conflicts (i.e., a conflictthat occurs, for example, when a store instruction from another threadwrites within a cache line in the footprint of a memory transaction, butdoes not actually alter the data being manipulated by the memorytransaction). Because conflicts are tracked on a per cache-line basisand not on a per-location basis, such false sharing conflicts cause thefailure of memory transactions that are not strictly required by thedefinition of a memory transaction, but must occur due to thelimitations of the conflict tracking implementation. ROTs, however, aremore resilient in the presence of such false sharing conflicts than thenon-ROT memory transactions that would have to be used in the absence ofsupport for ROTs.

With reference now to FIG. 9, an illustrative example of arepresentative ROT 900 is illustrated. ROT 900 may form, for example, aportion of a multiprocessor program.

ROT 900 begins with a unique instruction, tbegin_rot 902, whichidentifies the beginning of a ROT. Similar to a normal (i.e., non-ROT)memory transaction 400 of FIG. 4, the instruction immediately followingtbegin_rot instruction 902 is a branch instruction 904 that redirectsexecution to a failure handling routine in response to the ROT 900either failing or (as explained below) aborting under software control.Branch instruction 904 is followed by a transaction body 906, which maycontain transactional memory access (e.g., load and/or store) or otherinstructions, and possibly one or more tabort instruction(s) 910. Ifpresent, tabort instruction 910 directs execution of ROT 900 to beaborted and execution results of ROT 900 to be discarded. Although notillustrated in FIG. 9, ROT 900 may further optionally include bypassinstructions that determine if ROT 900 should be aborted (e.g., based ona variable value read from the distributed shared memory system by atransactional load of the ROT or the availability of a system resource)and that, responsive to the determination, either cause tabortinstruction 910 to be executed or cause execution to branch aroundtabort instruction 910 to one or more transactional instructionincluding tend instruction 908, which, when executed, causes ROT 900 tobe committed (and, in particular, makes the storage-modifying effects ofthe store instructions within transaction body 906 non-speculative).

If a tabort instruction 910 within a ROT 900 is executed, the executionresults of ROT 900 are discarded, a condition code register is updatedto indicate that a tabort instruction 910 caused the ROT to fail, andcontrol passes to branch instruction 904, which is taken based on thevalue present in the condition code register. Execution of a tabortinstruction 910 is the primary way in which the speculative executionresults of a ROT 900 are discarded and control is passed to the failhandler via branch instruction 904. Among other reasons, a ROT 900 (ornon-ROT memory transaction) may also fail and pass control to the failhandler via branch instruction 904 (or branch instruction 404) due to acapacity overflow (overflowing the capacity of TM logic 380) or due toexecution of an instruction (e.g., a cache-inhibited load or storeinstruction) that can have untracked side effects and therefore isinherently unable to be re-executed and consequently cannot legallyappear in a ROT or memory transaction (which may have to be executedseveral times to successfully commit).

Referring now to FIG. 10, there is illustrated a more detailed view ofTM tracking logic 381 in accordance with one embodiment. As depicted, TMtracking logic 381 includes a TM directory 1000, which contains a numberof entries 1002 for tracking the cache lines within the load and storefootprints of ROTs and/or non-ROT memory transactions. In the depictedembodiment, each entry 1002 within TM directory 1000 includes at leastfive fields: address tag field 1003, congruence class (CC) field 1004,way number field 1005, load valid (LV) field 1006, and store valid (SV)field 1008. Address tag field 1004, which in a typical embodiment storesthe high order bits of real memory addresses, indicates a specific cacheline that is in the transaction footprint of a memory transaction.Congruence class field 1004, which in a typical embodiment stores themid-order bits of real memory addresses, identifies the congruence classof directory 308 that holds directory information for the specific cacheline indicated by the associated address tag field 1003. Way numberfield 1005 further specifies the particular way of the identifiedcongruence class that holds directory information for the specific cacheline in the transaction footprint. SV field 1006 and LV field 1008,which each preferably include one bit per thread supported by theassociated processor core 200, respectively indicate whether the cacheline is part of the store footprint or load footprint of a memorytransaction and which thread that is executing the memory transaction.In at least one embodiment, LV field 1006 and SV field 1008 are mutuallyexclusive, meaning that, for a given entry 1002 and given thread, one orneither of the corresponding bits in LV field 1006 and SV field 1008 maybe set concurrently but not both. When all bits in both of fields 1006and 1008 are reset, the entry 1002 is invalid and no cache line is thenbeing tracked by that entry 1002.

For a non-ROT memory transaction, when a transactional load is presentedto TM logic 380 and there is no entry in TM directory 1000 for thetarget cache line of the transactional load, a new entry 1002 isallocated (possibly evicting an existing entry 1002), fields 1003-1005of the new entry 1002 are updated with the relevant informationregarding the target cache line, and the appropriate bit in LV field1006 is set. If, on the other hand, an existing entry 1002 is alreadytracking the target cache line (and therefore the appropriate bit ineither LV field 1006 or SV field 1008 is already set), no update to theexisting entry 1002 is made because the target cache line of thetransactional load is already being tracked.

As with a transactional load, if a transactional store of a non-ROTmemory transaction is presented to TM logic 380 and there is no entry inTM directory 1000 for the target cache line of the transactional store,a new entry 1002 is allocated (possibly evicting an existing entry1002), fields 1003-1005 of the new entry 1002 are updated with therelevant information regarding the target cache line, and theappropriate bit in SV field 1008 is set. If, on the other hand, anexisting entry 1002 is already tracking the target cache line and thebit in LV field 1006 for the relevant thread is set for that entry 1002,then the bit corresponding to that thread is reset in LV field 1006, andthe bit corresponding to the relevant thread is set in SV field 1008 toindicate that this cache line is now part of the store footprint for thethread's memory transaction. If the bit corresponding to the thread isalready set in SV field 1008 of the existing entry 1002, no update tothat entry 1002 is performed.

In response to a ROT or non-ROT memory transaction committing orfailing, TM tracking logic 381 clears the bit in LV field 1006 and SVfield 1008 for the thread executing the memory transaction.

For a ROT, TM tracking logic 381 updates TM directory 1000 as describedabove for transactional stores of non-ROT memory transactions. However,for loads within the ROT, TM tracking logic 381 does not update TMdirectory 1000 because the load footprint is not tracked for conflictsin a ROT. This behavior can be implemented in at least two ways. In afirst implementation, all non-transactional load and store operationstransmitted from a processor core 200 to its L2 cache 230 are identifiedas either being a non-transactional load or store, a non-ROTtransactional load or store, or as a ROT transactional load or store. Inthis case, TM tracking logic 381 ignores ROT transactional loads forpurposes of updating TM directory 1000. In another implementation, allnon-transactional loads and stores and ROT loads are identified as beingnon-transactional and are accordingly ignored by TM tracking logic 381for purposes of updating TM directory 1000. ROT transactional stores andnon-ROT transactional loads and stores are identified as beingtransactional, and TM tracking logic 381 accordingly updates TMdirectory 1000 as described above for non-ROT transactional loads andstores. In either implementation, TM tracking logic 381 preferably doesnot update TM directory 1000 for ROT transactional loads.

As further illustrated in FIG. 10, TM tracking logic 381 furtherincludes a set of comparators 1010. Each comparator 1010 compares thecongruence class field of the real address of a transactional ornon-transactional memory access request received from multiplexer M2with the congruence class indicated by the congruence class field 1004of a respective associated TM directory entry 1002. The match vector1020 output by comparators 1010 identifies the set of cache lines in oneor more transaction footprints that are at risk of being replaced fromthe congruence class accessed by the memory access request, absent someadjustment of the default replacement order of the cache lines in thatcongruence class by directory 308. In the depicted embodiment, an ORgate 1012 logically combines (i.e., ORs) all the bits comprising matchvector 1020 to produce a one-bit match indication 1022 indicatingwhether or not any matches were detected by comparators 1010.

TM tracking logic 381 further includes a load mask generator 1014 and astore mask generator 1016. Load mask generator 1014 receives as inputsmatch vector 1020 and the way number fields 1005 and LV fields 1006 ofTM directory entries 1002. Store mask generator 1016 similarly receivesas inputs match vector 1020 and the way number fields 1005 and SV fields1008 of TM directory entries 1002. Load mask generator 1014 produces asan output a load mask 1024 indicating (e.g., utilizing one bit per way)which way(s), if any, of the congruence class containing the targetcache line of the memory access request is/are in the load footprint ofan active memory transaction. Store mask generator 1016 produces acorresponding store mask 1026 indicating (e.g., utilizing one bit perway) which way(s), if any, of the congruence class containing the targetcache line of the memory access request is/are in the store footprint ofan active memory transaction. In the depicted embodiment, matchindication 1022, load mask 1024 and store mask 1026 collectively formreplacement order update message 383.

In one exemplary embodiment, load mask generator 1014 generates loadmask 1024 by first decoding the way number field(s) 1005 of the TMdirectory entry or entries 1002 (if any) that (1) is/are identified bymatch vector 1020 and (2) has/have any bit set in LV field 1006. Thedecode of way number field(s) 1005 produces a set of one-hot encodedvectors, which load mask generator 1014 then logically combines (e.g.,ORs) to obtain a possibly multi-hot load mask 1024 indicating zero ormore ways of the congruence class containing cache lines in the loadfootprint of memory transaction(s). Those skilled in the art willappreciate that store mask generator 1016 may generate store mask 1026in a like manner utilizing the contents of SV fields 1008 rather than LVfields 1006.

With reference now to FIG. 11, there is illustrated a high level logicalflowchart of a method of processing of a tend instruction terminating anon-ROT memory transaction or a ROT in accordance with one embodiment.For ease of understanding, like reference numerals are utilized todenote steps corresponding to those depicted in FIG. 8.

The process of FIG. 11 begins at block 800, for example, in response toinitiation of execution of a tend instruction within the LSU 202 of aprocessor core 200. LSU 202 then ensures at block 801 that all priorsuspend mode load instructions and all prior non-ROT transactional loadinstructions have their values bound. This check ensures the non-ROTtransactional load instructions are present in the memory transaction'sfootprint and that the suspend mode load instructions have obtainedtheir values. LSU 202 then determines at block 1100 whether or not thememory transaction terminated by the tend is a ROT or non-ROT memorytransaction. In response to a determination that the memory transactionis a non-ROT memory transaction, the process continues to block 802 andsubsequent blocks, which have been described.

Returning to block 1100, in response to a determination that the tendinstruction terminates a ROT, blocks 802, 804 and 806 are bypassed asunnecessary for a ROT, and control passes to block 1102. Block 1102depicts LSU 202 querying TM logic 380 whether a conflict for the ROT'sstore footprint was detected by TM tracking logic 381 (as opposed to aconflict on either the load or store footprint for a non-ROT memorytransaction). In response to TM logic 380 indicating a conflict has beendetected for the store footprint of the ROT, the process proceeds toblock 808, which depicts failing the ROT and invalidating its storefootprint as described above. In response to TM logic 380 indicating atblock 1102 that no conflict for the ROT has been detected, the processproceeds to block 810, which illustrates commitment of the ROT to thedistributed shared memory system as described above. It should again benoted that commitment of the ROT does not require observance ofcausality, as described above with reference to block 804. Followingeither block 808 or block 810, the process concludes at block 812.

In at least some embodiments, memory transactions, including ROTs and/ornon-ROT transactions, can be nested to any arbitrary depth, meaning thata ROT or a non-ROT transaction can contain one or more other memorytransactions. In at least some embodiments, so-called “flat nesting” ispreferably employed in which memory transactions contained within theoutermost memory transaction are subsumed by the outermost enclosingmemory transaction into a single memory transaction that either commitsas a whole or fails as a whole.

With reference now to FIG. 12, there is illustrated a representativenon-ROT memory transaction 1200, which contains a nested memorytransaction. Memory transaction 1200 may, for example, form a portion ofa multiprocessor program.

As before, an outermost or enclosing memory transaction 1200 begins at atbegin instruction 1202, which is followed by a branch instruction 1204that, if the indicated branch is taken, invokes execution of a firstfail handler routine. Outermost memory transaction 1200 additionallyincludes a transaction body 1206 that includes transactional memoryaccess (e.g., load and/or store) instructions and optionally one or moreadditional instructions.

Transaction body 1206 further includes a nested memory transaction 1208initiated by tbegin instruction 1210, which is followed by a branchinstruction 1216 that, if the indicated branch were to be taken, wouldredirect execution to a second fail handler routine associated withnested memory transaction 1208. Nested memory transaction 1208additionally includes a transaction body 1212 comprising one or moretransactional memory access (e.g., load and/or store) instructions, zeroor more optional additional instructions, and a tend instruction 1214.

In the example shown, the branch to the second fail handler routine willnever be taken because any conflict detected for memory transaction 1200will redirect execution to branch instruction 1204. Despite this fact, abranch instruction to a fail handler routine is typically provided forall memory transactions because of the difficulty in determining, apriori, whether or not a memory transaction will be executed as part ofa nested memory transaction. (For example, a given memory transactioncould be executed directly or could alternatively be executed as part ofa function call within another memory transaction. In the former case,the memory transaction would not be nested, while in the latter thememory transaction would be nested.)

To implement the “flat nesting” noted above, the load and storefootprints of memory transaction 1200 include the sets of memoryaddresses accessed by transactional load and store instructions,respectively, within transaction bodies 1206 and 1212. In addition, if atabort instruction were to be executed anywhere within memorytransaction 1200, control would transfer to branch instruction 1204. Inessence, tbegin instruction 1210 and tend instruction 1214 of nestedmemory transaction 1208 act like nop (noop) instructions, with theexception of causing updates to be made to a nesting level register andtransaction mode register as described below. It should be further notedthat memory transaction 1208 could be replaced by a ROT without anychange in the handling of the nested memory transactions.

In at least some embodiments, one or more ROT or non-ROT memorytransactions may also be nested within a ROT. For example, FIG. 13illustrates a ROT 1300 that begins at a tbegin_rot instruction 1302,which is followed by a branch instruction 1304 that, if the indicatedbranch is taken, invokes execution of a third fail handler routine. ROT1300 additionally includes a transaction body 1306 that includestransactional memory access (e.g., load and/or store) instructions,optionally one or more additional instructions, and optionally a tabortinstruction 1320. In the illustrated example, transaction body 1306further includes a nested non-ROT memory transaction 1208 as previouslydescribed. In one preferred embodiment, transactional memory accessinstructions within a ROT (e.g., ld A and st B) that precede a nestednon-ROT memory transaction (e.g., memory transaction 1208) are handledas ROT transactional memory accesses as described above with referenceto FIGS. 9-11, and transactional memory access instructions within a ROTthat fall within or follow a nested non-ROT memory transaction (e.g., ldC, ld D, st E, st F and ld G) are handled as non-ROT transactionalmemory accesses as described above with reference to FIGS. 7-8. In otherwords, once a nested memory transaction enters a non-ROT mode, either atthe initial tbegin instruction or at a subsequent nested tbegininstruction (such as tbegin instruction 1210 in ROT 1300), the memorytransaction remains in a non-ROT mode for the remainder of all thenested memory transactions, regardless of memory transaction type. Inthis manner, nested transactions retain the advantages of a ROT untilthe first, potentially nested, non-ROT transaction in the overallcollection of nested transactions is encountered.

To support nested memory transactions, TM tracking logic 381 ispreferably augmented as depicted in FIG. 14. As depicted, in addition tothe previously described TM directory 1000, TM tracking logic 381preferably includes, for each thread of processor core 200, a respectivetransaction mode register 1400 and a nesting level register 1402.Transaction mode register 1400 indicates a current mode of a memorytransaction under execution by the associated thread (e.g., ROT ornon-ROT). For nested memory transactions in which all the nestedtransactions are the same type, transaction mode register 1402 is set atthe outermost tbegin or tbegin_rot instruction and retains its valuethroughout the nested memory transaction. Nesting level register 1402indicates the current nesting depth of the memory transaction underexecution by the associated thread. At each tbegin or tbegin_rotinstruction within the nested memory transactions, nesting levelregister 1402 is incremented, and at each tend instruction within thenested transactions, nesting level register 1402 is decremented. If thenesting level exceeds the nesting depth that can be expressed by nestinglevel register 1402, the tbegin instruction fails at execution, settinga condition code, and execution of the fail handler routine is invoked.

Referring now to FIG. 15, there is depicted a high level logicalflowchart of the processing of transaction memory requests correspondingto instructions delimiting nested memory transactions (e.g., tbegin,tbegin_rot, and tend instructions) of possibly differing types (ROTand/or non-ROT memory transactions). The illustrated process begins atblock 1500 and proceeds to block 1502, which depicts TM logic 380determining if a tbegin or tbegin_rot request corresponding to a tbeginor tbegin_rot instruction initiating a memory transaction has beenreceived from the affiliated processor core 200. If not, the processpasses to block 1520, which is described below. If so, the processproceeds to block 1504, which depicts TM control logic 382 testingnesting level register 1402 to determine if nesting of memorytransactions has reached its maximum supported depth, for example, asdetermined by the size of nesting level register 1402. If so, TM controllogic 382 sets a condition code register in processor core 200 toindicate the error condition that the memory transaction nesting hasexceeded the maximum allowable depth (block 1506). The process thenreturns to block 1502, which has been described.

Returning to block 1504, in response to TM control logic 382 determiningthe maximum nesting level is not exceeded, TM tracking logic 381 setstransaction mode register 1400 to indicate the appropriate mode ofoperation (i.e., ROT or non-ROT) utilizing, for example, the processillustrated at blocks 1508-1516. In particular, TM tracking logic 381determines at block 1508 if the nesting level is zero (i.e., if thetbegin or tbegin_rot request corresponds to the initiation of anoutermost or enclosing memory transaction). If not, the process passesto block 1510, which is described below. If, however, the nesting levelis equal to zero, TM tracking logic 381 further determines at block 1512whether the memory transaction is a ROT (i.e., the memory transactionrequest is a tbegin_rot request). If not (i.e., the memory transactionrequest is a tbegin request corresponding to the tbegin instruction of anon-ROT memory transaction), the process proceeds to block 1516, whichillustrates TM tracking logic 381 setting transaction mode register 1400to indicate a non-ROT mode. If, on the other hand, TM tracking logic 381determines at block 1512 that the memory transaction request is atbegin_rot request corresponding to a tbegin_rot instruction initiatinga ROT, TM tracking logic 381 sets transaction mode register 1400 toindicate a ROT mode (block 1514). After either block 1514 or block 1516,the process then proceeds to block 1518, which is described below.

Referring now to block 1510, which is reached only if the detectedmemory transaction is a nested memory transaction enclosed withinanother enclosing memory transaction, TM tracking logic 381 determinesif the memory transaction request is a tbegin request corresponding to anested non-ROT memory transaction initiated by a tbegin instruction (asopposed to a tbegin_rot). If so, TM tracking logic 381 sets transactionmode register 1400 to indicate a transition to the non-ROT mode at block1516. If, however, TM tracking logic 381 determines at block 1510 thatthe memory transaction request is a tbegin_rot request corresponding toa tbegin_rot instruction initiating a nested ROT, the process thenproceeds directly to block 1518 without updating transaction moderegister 1400. To summarize, TM tracking logic 381, responsive to memorytransaction requests (i.e., tbegin and tbegin_rot requests)corresponding to tbegin and tbegin_rot instructions, sets transactionmode register 1400 to the transaction mode corresponding to the type ofthe outermost memory transaction (ROT or non-ROT) and then setstransaction mode register 1400 to non-ROT mode in response toencountering any subsequent non-ROT memory transaction nested within theoutermost memory transaction.

At depicted at block 1518, TM control logic 381, responsive to thetbegin or tbegin_rot request corresponding to a tbegin or tbegin_rotinstruction initiating a memory transaction, also increments nestinglevel register 1402 to indicate the present depth of nesting. Theprocess then returns to block 1502, which has been described.

Referring now to block 1520, TM tracking logic 381 determines whetherthe received request is a tend request corresponding to execution of atend instruction that terminates a memory transaction. If not, theprocess returns to block 1502 to await receipt of the next tbegin,tbegin_rot, or tend request, as has been described. If, however, TMtracking logic 381 determines that the memory transaction request is atend request generated by execution of a tend instruction in theaffiliated processor core 200, TM tracking logic 381 queries nestinglevel register 1402 to determine if the current nesting level is greaterthan one, indicating that the tend instruction does not terminate theoutermost memory transaction of a collection of nested memorytransactions. If so, TM tracking logic 381 simply decrements nestinglevel register 1402 to update the current nesting depth (block 1552). Inother respects, the tend request and associated tend instruction aretreated as a no-ops, as noted above. The process then returns to block1502.

Returning to block 1550, if nesting level register 1402 has a value notgreater than one, the process proceeds to block 1554, which depicts TMtracking logic 381 determining if the nesting level indicated by nestinglevel register 1402 equals one, indicating that the tend instructioncorresponding to the received tend request terminates the outermostmemory transaction. If so, the tend request is processed according tothe process described above with reference to FIG. 11 (block 1556). Inaddition, TM tracking logic 381 decrements the nesting level indicatedby nesting level register 1402, as described above with reference toblock 1552.

Returning to block 1554, if the nesting level indicated by nesting levelregister 1402 is not one, then the nesting level must be zero (i.e., notone or greater than one). This condition indicates that an error hasoccurred due to the fact that a tend instruction has been executedwithout a corresponding tbegin or tbegin_rot instruction. Accordingly,TM tracking logic 381 sets an error indication to indicate detection ofthis error (block 1558). Thereafter, the process returns to block 1502to await the next tbegin, tbegin_rot, or tend request.

Referring now to FIG. 16, there is depicted a high level logicalflowchart of a exemplary method by which a cache memory (e.g., L2 cache230) protects the transaction footprint of a memory transaction fromvictimization by selectively updating replacement order (e.g., LRU)information in a cache directory. By protecting the transactionfootprint of the memory transaction in this manner, cache lines touchedby the memory transaction tend to remain resident in L2 cache 230 ratherthan being castout due to capacity constraints, thus increasing thelikelihood that the memory transaction will complete successfully.

The process begins at block 1600 and then proceeds to block 1602, whichillustrates the directory 308 of an L2 cache 230 awaiting receipt, viamultiplexer M2, of a next memory access request. In response to receiptof a memory access request, directory 308 determines, for example, byreference to match indication 1022 of the replacement order updatemessage 383 for the memory access request, whether or not the congruenceclass field of the real address specified by the memory access requestmatches the congruence class specified in one or more of the entries1002 of TM directory 1000 (block 1604). If not, directory 308 updatesthe replacement order of the cache lines in the relevant congruenceclass in accordance with the default replacement policy of directory 308(e.g., LRU), as shown at block 1606. For example, in accordance with theLRU replacement policy, the way containing the LRU cache line isselected for victimization (if replacement of a cache line isnecessary), the way containing the target cache line of the memoryaccess request is made MRU, and if the target cache line was not alreadyMRU, each other way is demoted one position (e.g., MRU to MRU−1, etc.)in the replacement order. Following block 1606, the process returns toblock 1602, and directory 308 awaits receipt of the next memory accessrequest.

Returning to block 1604, in response to directory 308 determining thatthe congruence class field of the real address specified by the memoryaccess request matches the congruence class specified in one or more ofthe entries 1002 of TM directory 1000, directory 308 forms a working setof ways in the congruence class to which preference is to be given whenupdating the replacement order of the congruence class. In theembodiment given in FIG. 16, directory 308 selectively determines theformation of the working set based on load mask 1024 and store mask1026. The addition of ways to the working set can further be performedbased on a software or hardware-controlled operation mode of directory308. For example, the operation mode of directory 308 can specify that(1) only ways containing cache lines in a store footprint of a memorytransaction are included in the working set, (2) only ways containingcache lines in a load footprint of a memory transaction are included inthe working set, or (3) ways contained in either the load footprint orthe store footprint of a memory transaction are included in the workingset. At blocks 1610-1612, directory 308 adds to the working set the waysthat store mask 1026 indicates are in the store footprint of a memorytransaction, if doing so is indicated by the operating mode of directory308. Similarly, at blocks 1614-1616, directory 308 adds to the workingset the ways that load mask 1024 indicates are in the load footprint ofa memory transaction, if doing so is indicated by the operating mode ofdirectory 308.

At block 1620, directory 308 determines whether or not the working setof ways that are to be given preference in the replacement order updateis empty. If so, the process proceeds from block 1620 to block 1606,which has been described. If, however, directory 308 determines at block1620 that the working set of ways is not empty, directory 308 performsthe replacement order update of the congruence class, giving preferenceto the ways in the working set (block 1622). For example, in oneembodiment in which a modified LRU replacement policy is implemented bydirectory 308, the way containing the LRU cache line is selected forvictimization (if replacement of a cache line is necessary), and the waycontaining the target cache line of the memory access request is madeMRU, as in the default replacement policy. If possible, directory 308also promotes each way in the working set in its relative replacementordering with respect to other ways in the working set to make the cachelines contained in those ways less likely to be selected forreplacement. Thus, assuming these ways do not contain the target cacheline (which is made MRU), the most recently used way in the working setis made MRU−1, the second most recently used way in the working set ismade MRU−2, etc. Directory 308 demotes ways of the congruence class, ifany, that are excluded from the working set to replacement positionsbelow those of the ways in the working set (i.e., positions closer toLRU). Thus, for example, if the working set contains N ways, the wayexcluded from the working set that contains the most recently used cacheline is demoted to MRU−1-N, the way containing the next most recentlyused cache line is updated to MRU−2-N, etc. As will be appreciated bythose skilled in the art, many alternative replacements orderings can beemployed to reduce the likelihood that a cache line in the transactionfootprint of a memory transaction is selected for replacement by thereplacement policy. Following block 1622, the process of FIG. 16 returnsto block 1602.

One alternative to the disclosed technique of maintaining cache lines inthe transaction footprint in cache is to simply eliminate wayscontaining cache lines in the transaction footprint from selection forvictimization. However, this alternative technique increases thecritical timing path of accesses to L2 cache 230 and requires greaterdie area to implement the requisite logic. Consequently, the lessprecise technique of promoting the replacement ordering of cache linesin the transaction footprint is preferred.

With reference now to FIG. 17, there is depicted a block diagram of anexemplary design flow 1700 used for example, in semiconductor IC logicdesign, simulation, test, layout, and manufacture. Design flow 1700includes processes, machines and/or mechanisms for processing designstructures or devices to generate logically or otherwise functionallyequivalent representations of the design structures and/or devicesdescribed above and shown in FIGS. 1-3, 7, 10 and 14. The designstructures processed and/or generated by design flow 1700 may be encodedon machine-readable transmission or storage media to include data and/orinstructions that when executed or otherwise processed on a dataprocessing system generate a logically, structurally, mechanically, orotherwise functionally equivalent representation of hardware components,circuits, devices, or systems. Machines include, but are not limited to,any machine used in an IC design process, such as designing,manufacturing, or simulating a circuit, component, device, or system.For example, machines may include: lithography machines, machines and/orequipment for generating masks (e.g. e-beam writers), computers orequipment for simulating design structures, any apparatus used in themanufacturing or test process, or any machines for programmingfunctionally equivalent representations of the design structures intoany medium (e.g. a machine for programming a programmable gate array).

Design flow 1700 may vary depending on the type of representation beingdesigned. For example, a design flow 1700 for building an applicationspecific IC (ASIC) may differ from a design flow 1700 for designing astandard component or from a design flow 1700 for instantiating thedesign into a programmable array, for example a programmable gate array(PGA) or a field programmable gate array (FPGA) offered by Altera® Inc.or Xilinx® Inc.

FIG. 17 illustrates multiple such design structures including an inputdesign structure 1020 that is preferably processed by a design process1710. Design structure 1720 may be a logical simulation design structuregenerated and processed by design process 1710 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 1720 may also or alternatively comprise data and/or programinstructions that when processed by design process 1710, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 1720 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer. When encoded on a machine-readable datatransmission, gate array, or storage medium, design structure 1720 maybe accessed and processed by one or more hardware and/or softwaremodules within design process 1710 to simulate or otherwise functionallyrepresent an electronic component, circuit, electronic or logic module,apparatus, device, or system such as those shown in FIGS. 1-3, 7, 10 and14. As such, design structure 1720 may comprise files or other datastructures including human and/or machine-readable source code, compiledstructures, and computer-executable code structures that when processedby a design or simulation data processing system, functionally simulateor otherwise represent circuits or other levels of hardware logicdesign. Such data structures may include hardware-description language(HDL) design entities or other data structures conforming to and/orcompatible with lower-level HDL design languages such as Verilog andVHDL, and/or higher level design languages such as C or C++.

Design process 1710 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures shown in FIGS. 1-3, 7, 10 and 14 togenerate a netlist 1780 which may contain design structures such asdesign structure 1720. Netlist 1780 may comprise, for example, compiledor otherwise processed data structures representing a list of wires,discrete components, logic gates, control circuits, I/O devices, models,etc. that describes the connections to other elements and circuits in anintegrated circuit design. Netlist 1780 may be synthesized using aniterative process in which netlist 1780 is resynthesized one or moretimes depending on design specifications and parameters for the device.As with other design structure types described herein, netlist 1780 maybe recorded on a machine-readable storage medium or programmed into aprogrammable gate array. The medium may be a non-volatile storage mediumsuch as a magnetic or optical disk drive, a programmable gate array, acompact flash, or other flash memory. Additionally, or in thealternative, the medium may be a system or cache memory, or bufferspace.

Design process 1710 may include hardware and software modules forprocessing a variety of input data structure types including netlist1780. Such data structure types may reside, for example, within libraryelements 1730 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 90 nm, etc.). The data structure types may further include designspecifications 1740, characterization data 1750, verification data 1760,design rules 1770, and test data files 1785 which may include input testpatterns, output test results, and other testing information. Designprocess 1710 may further include, for example, standard mechanicaldesign processes such as stress analysis, thermal analysis, mechanicalevent simulation, process simulation for operations such as casting,molding, and die press forming, etc. One of ordinary skill in the art ofmechanical design can appreciate the extent of possible mechanicaldesign tools and applications used in design process 1710 withoutdeviating from the scope and spirit of the invention. Design process1710 may also include modules for performing standard circuit designprocesses such as timing analysis, verification, design rule checking,place and route operations, etc.

Design process 1710 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 1720 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 1790.Design structure 1790 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g., information stored in a IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures). Similar to designstructure 1720, design structure 1790 preferably comprises one or morefiles, data structures, or other computer-encoded data or instructionsthat reside on transmission or data storage media and that whenprocessed by an ECAD system generate a logically or otherwisefunctionally equivalent form of one or more of the embodiments of theinvention shown in FIGS. 1-3, 7, 10 and 14. In one embodiment, designstructure 1790 may comprise a compiled, executable HDL simulation modelthat functionally simulates the devices shown in FIGS. 1-3, 7, 10 and14.

Design structure 1790 may also employ a data format used for theexchange of layout data of integrated circuits and/or symbolic dataformat (e.g., information stored in a GDSII (GDS2), GLI, OASIS, mapfiles, or any other suitable format for storing such design datastructures). Design structure 1790 may comprise information such as, forexample, symbolic data, map files, test data files, design contentfiles, manufacturing data, layout parameters, wires, levels of metal,vias, shapes, data for routing through the manufacturing line, and anyother data required by a manufacturer or other designer/developer toproduce a device or structure as described above and shown in FIGS. 1-3,7, 10 and 14. Design structure 1790 may then proceed to a stage 1795where, for example, design structure 1790: proceeds to tape-out, isreleased to manufacturing, is released to a mask house, is sent toanother design house, is sent back to the customer, etc.

As has been described, in at least one embodiment, a processing unitincludes a processor core and a cache memory. Entries in the cachememory are grouped in multiple congruence classes. The cache memoryincludes tracking logic that tracks a transaction footprint includingcache line(s) accessed by transactional memory access request(s) of amemory transaction. The cache memory, responsive to receiving a memoryaccess request that specifies a target cache line having a targetaddress that maps to a congruence class, forms a working set of ways inthe congruence class containing cache line(s) within the transactionfootprint and updates a replacement order of the cache lines in thecongruence class. Based on membership of the at least one cache line inthe working set, the update promotes at least one cache line that is notthe target cache line to a replacement order position in which the atleast one cache line is less likely to be replaced.

While various embodiments have been particularly shown and described, itwill be understood by those skilled in the art that various changes inform and detail may be made therein without departing from the spiritand scope of the appended claims and these alternate implementations allfall within the scope of the appended claims. For example, althoughembodiments employing a modified LRU replacement policy have beendescribed, those skilled in the art should appreciated that theinventive techniques disclosed herein can also be applied to systemsemploying other replacement policies (e.g., pseudo-LRU, MRU, etc.). Inaddition, although aspects have been described with respect to acomputer system executing program code that directs the functions of thepresent invention, it should be understood that present invention mayalternatively be implemented as a program product including acomputer-readable storage medium storing program code that can beprocessed by a data processing system. The computer-readable storagemedium can include volatile or non-volatile memory, an optical ormagnetic disk, or the like, but excludes transitory signal media.

As an example, the program product may include data and/or instructionsthat when executed or otherwise processed on a data processing systemgenerate a logically, structurally, or otherwise functionally equivalentrepresentation (including a simulation model) of hardware components,circuits, devices, or systems disclosed herein. Such data and/orinstructions may include hardware-description language (HDL) designentities or other data structures conforming to and/or compatible withlower-level HDL design languages such as Verilog and VHDL, and/or higherlevel design languages such as C or C++. Furthermore, the data and/orinstructions may also employ a data format used for the exchange oflayout data of integrated circuits and/or symbolic data format (e.g.information stored in a GDSII (GDS2), GLI, OASIS, map files, or anyother suitable format for storing such design data structures).

What is claimed is:
 1. A method of data processing in a data processing system having a processor core and a shared memory system including a cache memory, the method comprising: the cache memory tracking a transaction footprint including one or more cache lines accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core; in response to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory: the cache memory forming a working set of ways in the congruence class containing one or more cache lines within the transaction footprint; and the cache memory updating a replacement order of the cache lines in the congruence class, wherein the updating includes promoting at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set.
 2. The method of claim 1, wherein the updating includes updating the replacement order of the target cache line to most recently used (MRU).
 3. The method of claim 2, wherein the updating includes updating the replacement order of a most recently used cache line in the transaction footprint other than the target cache line to MRU−1.
 4. The method of claim 1, wherein the forming includes a directory of the cache memory forming the working set in response to a replacement order update message from transactional memory tracking logic within the cache memory.
 5. The method of claim 1, wherein: the transaction footprint includes a load footprint and a store footprint; and the updating further comprises excluding from the promoting one of a set including the load footprint and the store footprint.
 6. The method of claim 1, and further comprising: in response to formation of an empty working set, updating the replacement order of the cache lines in the congruence class in accordance with a default replacement policy. 